Semiconductor manufacturing
Chip manufacturing turns quartz into eleven-nines silicon and then into a working processor the size of a stamp, through roughly a thousand tightly controlled steps at near-atomic precision.
Follow a wafer through all ten stages of the fab · run the yield math that prices every chip · map the industry's six roles and its real chokepoints.
A switch, repeated fifty billion times
At its foundation, a chip repeats one device at enormous scale: the transistor, an electronic switch with no moving parts. Silicon is useful because it is a semiconductor; carefully added impurities, or dopants, allow engineers to control when it conducts. Billions of transistors arranged into logic produce computation.
The basic device is easier to describe than to manufacture. Modern transistors operate at dimensions where atomic-scale variation matters. Producing them requires cleanrooms, vacuum systems, ultrapure materials, precision optics, plasma chemistry, metrology, and process control working as one system. The industry calls the facility a fab.
Keep one mental model: chips are built layer by layer. Pattern, deposit, etch, measure, and repeat (dozens of times) until a three-dimensional electrical system emerges on a polished silicon wafer. The same few operations repeat on every layer, and each new layer must align to the ones below it within nanometers.
Ten stops, one thousand steps
Click a stage. The dot tracks roughly where you are in a 2–4 month fab cycle: remembering that the middle stages loop dozens of times.
The yield game
Every defect on a wafer kills whatever die it lands on. So yield falls roughly as e−A·D₀ (die area times defect density) which makes die size the most expensive decision in chip design. Drag the sliders: with small dies, most of the wafer survives the same defect density; grow the die toward the reticle limit and the share of good dice on the same wafer falls steeply. This relationship underlies binning, chiplets, and the high cost of AI-scale dies.
300 mm wafer map
…Model: Y = e^(−A·D₀) (Poisson), 3 mm edge exclusion. Mature advanced-node defect densities are commonly reported around 0.05–0.1/cm²; ~850 mm² is the practical reticle limit (~26 × 33 mm): the size class of the largest AI dies. Illustrative, not any specific product.
The words in the cleanroom
The division of labor
The industry divides into six roles, and no single company covers all of them. Tap through them below.
The structure matters because it concentrates: one dominant EUV maker, a handful of leading-edge foundries, three EDA firms, a short list of resist and wafer suppliers. Semiconductor geopolitics is mostly the map of these bottlenecks, which is why chips are treated as strategic infrastructure and why fabs anchor the industrial policy of every major economy.
Common misconceptions
Node names stopped measuring physical features years ago: they're generation labels, defined differently by each manufacturer. Density and performance per watt are the honest comparisons.
A single device may be designed in California, printed in Taiwan on Dutch machines with Japanese chemicals, packaged in Malaysia, and tested in Vietnam: crossing borders dozens of times.
Classic planar scaling ended, but density keeps climbing through 3D transistors, stacking, and chiplets, while cost-per-transistor no longer falls the way it did.
Wafers travel by ceiling robot, but a leading-edge fab employs thousands of engineers and technicians. Talent (not tools) is repeatedly cited as the binding constraint on new fab regions.
Four questions before you go
Where to go next
Sources & methodology
Figures are teaching values, hedged where practice varies. Reference points: IRDS (International Roadmap for Devices and Systems: successor to ITRS) and SIA/SEMI industry data; ASML EUV system disclosures (architecture and the High-NA transition); ISO 14644 (cleanroom classes); the ~26 × 33 mm reticle field limit (industry standard); Poisson and Murphy yield models with defect densities as commonly reported for mature advanced nodes; mask-layer counts and 2–4 month cycle times as commonly reported for advanced logic; Czochralski growth and eleven-nines silicon purity (electronic-grade standard); FinFET (2011) and gate-all-around transitions per manufacturer disclosures. The wafer map uses Y=e^(−A·D₀) with a seeded random layout, 3 mm edge exclusion: illustrative, not any specific product.
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